1. Field of the Invention
The present invention generally relates to phase locked loop (PLL) circuits and semiconductor devices, and more particularly to a PLL circuit that operates even at a relatively low power supply voltage and to a semiconductor device including such a PLL circuit.
2. Description of the Related Art
FIG. 1 is a diagram showing an example of a conventional PLL circuit. A PLL circuit 101 has a phase comparator 111 that receives an input signal and a feedback signal which will be described later, a charge pump 112 that is controlled by an output of the phase comparator 111, a lowpass filter (LPF) 113, a voltage controlled oscillator (VCO) 114, and a frequency divider 115. The LPF 113 is made up of a resistor R1 and capacitors C1 and C2. An output signal of the VCO 114 is subjected to a 1/N frequency-division by the frequency divider 115, and is fed back to the phase comparator 111 as the feedback signal referred above. In FIG. 1, VDD denotes a power supply voltage.
When designing the PLL circuit 101, measures are taken so as to sufficiently secure stability of the PLL circuit 101. In order to analyze the stability of the PLL circuit 101, an absolute value |Gop| of an open gain Gop of the PLL and a phase Φ of the PLL, obtained from the following formulas (1) through (3), are used. In the following formulas (1) through (3), Icp denotes the current flowing through the charge pump 112, S=jω (ω denotes the frequency), R1 denotes the resistance of the resistor R1, C1 and C2 respectively denote the capacitances of the capacitors C1 and C2, and KVCO denotes the gain of the VCO 114.Gop=(Icp/2π)×[(1+SR1C1)/{S(C1+C2)(1+S(R1C1C2)/(C1+C2))}]×(2π×KVCO)/S  (1)|Gop|=(1/ω2)×{(Icp×KVCO)/(C1+C2)}{(1+ω2·R12C12)1/2/1}×[1/{1+ω2·(R1C1C2)2/(C1+C2)2}1/2]  (2)Φ=−π+tan−1(ω·R1C1)−tan−1{ω·(R1C1C2)/(C1+C2)}  (3)
FIG. 2 is a diagram showing a gain versus frequency characteristic of the formula (2), and FIG. 3 is a diagram showing a phase versus frequency characteristic of the formula (3). In FIG. 3, a difference between the phase at a crossover frequency where the open gain Gop becomes 0 and the phase of −180° is referred to as a phase margin. When designing the PLL circuit 101, the parameters of the PLL are determined so that this phase margin becomes 45°.
Due to the size reduction of semiconductor integrated circuits, the tendency is for the power supply voltage to becomes lower. For this reason, there is a tendency for the input voltage range of the VCO 114 within the PLL circuit 101 of the semiconductor integrated circuit to become narrower. Hence, when designing the VCOs 114 having the same performance, the tendency is for the gain KVCO of the VCO 114 to become larger as the input voltage range of the VCO 114 becomes narrower.
FIG. 4 is a diagram showing a relationship of the output frequency and the input voltage of the VCO 114. In FIG. 4, Vth denotes a threshold value of the input voltage of the VCO 114. The oscillation range of the VCO 114 is determined by the threshold voltage Vth and a power supply voltage VDDH of the VCO 114. For example, if the power supply voltage VDDH of the VCO 114 decreases to VDDL, the gain KVCO increases and becomes larger when designing the VCOs 114 in the same oscillation guarantee range. Since the gain KVCO appears in the numerator of the formula (2), the crossover frequency in FIG. 2 becomes high, and the phase margin in FIG. 3 consequently becomes small. Accordingly, when designing the VCOs 114 having the same performance, the capacitance of the capacitor C1 must be made large in order to reduce the crossover frequency by an amount corresponding to the increase of the gain KVCO, but as a result, the area occupied by the capacitor C1 becomes large to thereby preventing the size reduction of the semiconductor integrated circuits.
Therefore, in the conventional PLL circuit, when the power supply voltage becomes low due to the size reduction of the semiconductor integrated circuit, it becomes necessary to increase the gain of the VCO to a large value. For this reason, there were problems in that the capacitance of the capacitor within the LPF increases by the amount corresponding to the increase of the gain of the VCO, and that the area occupied by the capacitor becomes large to thereby prevent the size reduction of the semiconductor integrated circuit. Furthermore, there was a problem in that the power consumption of the PLL circuit becomes large due to the large gain of the VCO.